1. Field of the Invention
The present invention relates to a failure analyzing method and a failure analyzing apparatus which detect a feature of failures from a fail bit map (a map showing addresses of a semiconductor device at which failures have been detected) created, for example, in a testing or inspection process of a semiconductor integrated circuit or the like.
2. Description of the Related Art
In a testing or inspection process of a semiconductor integrated circuit, the test or inspection result of xe2x80x9can integrated circuit in which memory cells are arranged in an arrayxe2x80x9d such as a DRAM (Dynamic Random Access Memory) and the like is constituted by pass bits each of which means a normally operating portion and failure bits each of which means an abnormally operating portion, i.e., a failure or defect. This test result is outputted as a fail bit map from a semiconductor testing or inspecting apparatus.
It is very important in improving the production yield of semiconductor products to specify failure addresses and the number of failures of the tested integrated circuit utilizing the fail bit map, and to analyze a cause of occurrence thereof and feed it back to the manufacturing line. Usually, the analysis of a fail bit map is realized by creating a visual binary image constructed such that, for example, a pass bit has a value xe2x80x9c1xe2x80x9d and a failure bit has a value xe2x80x9c0xe2x80x9d on a fail bit map display. The displayed information is observed by a person or operator who analyzes the position and cause of failure. However, as a high integration density of circuits goes on, the fail bit map becomes huge. For example, a fail bit map having 1024xc3x971024 bits cannot be displayed on a screen of a display device having a resolution of 512xc3x97512 pixels. For this reason, a fail bit map must be displayed on several screens by dividing the fail bit map into several pieces.
Since a person or operator must precisely observe any failure which may occur at any address of an image (map) having a big size, the analysis work is very troublesome. In addition, it is anticipated that an error probably occurs in the measurements of failure addresses and of the number of failures. Therefore, there is an increased need for a technology for displaying a fail bit map having a large number of data to be displayed, as in the case of a memory device having its capacity of equal to or larger than 1 megabit (Mbit), on a single screen of the display to make the analysis work easy, or a technology for automating the analysis work for the fail bit map itself, which has conventionally been performed by a person.
Heretofore, in order to display a fail bit map having a large number of display data on a single screen of the display, there has been utilized a technology for compressing and displaying a binary image of a fail bit map. In this technology, a fail bit map is divided into a plurality of blocks each having, for example, 2xc3x972 bits, and each block is displayed by one pixel. Each pixel is displayed by use of a different color from one another depending on the number of failure bits contained in the corresponding block. For example, if each block has 2xc3x972 bits, five colors are used to display the compressed fail bit map since the number of failure bits in one block is five from 0 to 4. By this procedure, a fail bit map having 1024xc3x971024 bits can be displayed on the screen of a display device having 512xc3x97512 pixels, and hence it is possible that such fail bit map having a large volume of data can be analyzed on a single screen. In addition, in the case that the integration density of circuits is increased even more, and that a fail bit map having 2048xc3x972048 bits should be analyzed, it is possible to analyze such fail bit map on a single screen of the display by dividing and compressing the fail bit map into a plurality of blocks, each having 4xc3x974 bits.
Next, problems probably occurring in the case of utilizing the technology for compressing and displaying a fail bit map will be described. In the case of compressing a fail bit map having, for example, 2048xc3x972048 bits into 512xc3x97512 pixels, one pixel must have information of 4xc3x974 bits. Since each pixel is classified by a color depending on the number of failures contained therein, the pixels of the fail bit map have to be classified using 17 different colors corresponding to the failure number of 0 to 16 in this case. From now on, as the memory capacity of a memory device is further increased such as 256 Mbits, 1 gigabit (Gbit) or the like, the number of colors required for displaying each pixel is increased in proportion to the memory capacity of memory device. If the number of colors for displaying each pixel is increased, a problem occurs that it is difficult to grasp the number of failure bits from the color of each pixel. In addition, in the prior art, since a compressed fail bit map is displayed on a screen of the display and the displayed fail bit map is ultimately observed by a person, the problem remains unsolved that the failure addresses and the number of failures must be precisely measured by human eyes in detail.
It is an object of the present invention to provide a failure analyzing method which is capable of automatically performing, from a created fail bit map, an analysis work of the failure addresses of the map and the number of failures therein, which has been conventionally performed by a person.
It is an another object of the present invention to provide a failure analyzing apparatus which is capable of automatically performing, from a fail bit map, an analysis work of the failure addresses of the map and the number of failures therein.
In a first aspect of the present invention, in order to attain the above object, there is provided a failure analyzing apparatus for extracting failure information from a fail bit map comprising: two-dimensional Wavelet-transforming means for applying two-dimensional Wavelet-transform to an inputted fail bit map.
In a second aspect of the present invention, in order to attain the above object, there is provided a failure analyzing apparatus for extracting failure information from a fail bit map comprising: two-dimensional Wavelet-transforming means for applying two-dimensional Wavelet-transform to an inputted fail bit map; and histogram producing means for adding up Wavelet coefficients in Y direction with respect to X directional high-pass and Y directional low-pass information in the result of two-dimensional Wavelet-transform to create an X address histogram, and for adding up Wavelet coefficients in X direction with respect to X directional low-pass and Y directional high-pass information in the result of two-dimensional Wavelet-transform to create a Y address histogram.
In a preferred embodiment, the failure analyzing apparatus further includes: failure information outputting means for defining as failure addresses an X address having an added value other than zero in the X address histogram obtained by said histogram producing means and a Y address having an added value other than zero in the Y address histogram obtained by said histogram producing means, and outputting the added value of said X address in the histogram and the added value of said Y address in the histogram as the numbers of failures respectively.
In addition, it is preferred that the failure analyzing apparatus further includes: decision means for determining whether or not the number of failures is equal to the amount of X address or Y address of the inputted fail bit map; means for outputting, when said decision means determines that the number of failures is equal to the amount of X address or Y address of the inputted fail bit map, information representing that the failures extend over the corresponding entire X address or Y address; and failure address detecting means for scanning, when said decision means determines that the number of failures is not equal to the amount of X address or Y address of the inputted fail bit map, the X address or the Y address in which the failures are present in the inputted fail bit map or in the Wavelet-transformed result of the fail bit map, thereby to detect a starting address of the failures and an ending address of the failures.
Further, the failure analyzing apparatus may include: determining means for determining whether or not the number of failures is one; and one bit failure determining means for determining, when said determining means determines that the number of failures is one, whether or not the failure is a one bit failure.
It is preferred that a basic function of the two-dimensional Wavelet-transforming means is a redundant Haar-Wavelet-transform in which a shift parameter for Haar-Wavelet-transform is set to 1.
In a third aspect of the present invention, in order to attain the above object, there is provided a failure analyzing method comprising the steps of: applying two-dimensional Wavelet-transform to an inputted fail bit map; adding up Wavelet coefficients, with respect to a component including high-pass information in the result of the two-dimensional Wavelet-transform, in a specified direction of high-pass information producing process to create a histogram; and analyzing a failure address and the number of failures from the histogram.
In a preferred embodiment, the failure analyzing method further includes the step of; finding a failure address based on an address having an added value other than zero in the histogram, and finding the number of failures for the failure bit from the added value in the histogram of the address corresponding to the failure address.
In addition, it is preferred that the failure analyzing method further includes the steps of: determining whether or not the failure bit of the found failure address extends over the corresponding entire address in the fail bit map from the number of the failure bit; and scanning, when the failure bit of the found failure address does not extend over the corresponding entire address in the fail bit map, the inputted fail bit map or the Wavelet-transformed result at the failure address to find a starting address of the failures and an ending address of the failures as well as the number of failures present between the starting address and the ending address.
Further, the failure analyzing method may include the step of: adding up Wavelet coefficients, when the failure number of the failure bit is one, in the direction of high-pass information producing process orthogonal to the specified direction of high-pass information producing process to create a second histogram, applying a similar processing to said second histogram to find a failure address and the number of failures, and determining whether the failure is one bit failure or not using the failure address and the number of failures as well as the previously found failure address and the number of failures.